AnalogCoder: Analog Circuit Design via Training-Free Code Generation

Analog circuit design is a vital component of modern semiconductor technology, enabling electronic devices to interface with physical signals such as sound, light, and temperature. Despite recent breakthroughs using Large Language Models to automate digital chip design, analog design has remained heavily reliant on scarce human expertise. This lag stems from the high complexity of analog components, the need for precise physical-level representations rather than high-level abstractions, and a severe scarcity of analog circuit code in public training data. As a result, manually designing analog circuit netlists remains a slow, labor-intensive, and error-prone bottleneck in chip development.

The article introduces and evaluates AnalogCoder, the first training-free Large Language Model agent developed specifically for automated analog integrated circuit design. The main objective is to demonstrate that an artificial intelligence agent can successfully generate functional analog circuits from natural language requirements by framing circuit design as executable Python code generation.

To bridge the data and domain gap, the approach relies on Python and the PySpice library, bypassing the poorly represented specialized circuit syntax (such as standard SPICE netlists) in favor of a programming language in which models exhibit deep fluency. The framework incorporates domain-specific prompt engineering, including step-by-step reasoning and one-shot examples, alongside a four-stage automated feedback flow that evaluates requirement adherence, operating point stability, DC signal sweeps, and functional circuit performance over up to three iterative repair attempts. Furthermore, successful circuits are archived into a reusable modular tool library that can be queried and retrieved to construct complex, multi-stage composite designs. The authors evaluated this system across a newly constructed benchmark comprising 24 diverse analog design tasks ranging from basic amplifiers to composite oscillators and operational amplifier systems, comparing multiple commercial and open-source models.

AnalogCoder achieved the highest overall success rate, autonomously solving 20 out of 24 benchmark circuit challenges and attaining an average first-attempt success rate (Pass@1) of 66.1%. By comparison, standard GPT-4o without the modular tool library solved 15 tasks with a 54.2% Pass@1 rate, while top open-source models such as DeepSeek-V2 and Llama-3-70B solved 13 and 11 tasks, respectively. The tool library proved essential for complex composite architectures: standard models failed on composite tasks like integrators, differentiators, and adders, whereas AnalogCoder designed them with high reliability by reusing previously verified sub-circuits. Ablation studies demonstrated that generating Python instead of native SPICE, applying automated error feedback, and providing structured reasoning prompts each provided substantial performance improvements, with fine-tuning offering minor syntax consistency but limited gains on complex tasks.

These findings indicate that generative AI can dramatically lower technical barriers and compress development timelines in analog chip design. By enabling automated netlist synthesis without specialized model retraining, organizations can reduce engineering labor costs, accelerate time-to-market, and allow non-specialist engineers to prototype functional analog blocks. Crucially, modular reuse and closed-loop simulation feedback mitigate the risk of common design flaws, such as disconnected nodes and inactive transistors.

Organizations exploring automated circuit synthesis should consider deploying closed-loop code generation pipelines that leverage high-level languages and modular sub-circuit registries rather than attempting direct hardware description generation from scratch. For immediate applications, decision-makers should pair functional generative agents with established downstream optimization tools for fine-grained parameter tuning. Further research is recommended to expand sub-circuit libraries and evaluate the framework on larger, production-grade mixed-signal systems.

Confidence in these findings is supported by standardized multi-trial simulation benchmarks across numerous leading foundation models. However, readers should note that the current scope focuses strictly on functional circuit topology creation rather than deep transistor sizing and layout optimization. Additionally, four of the most complex benchmark circuits (including phase-locked loops and voltage-controlled oscillators) were not solved by any evaluated model, indicating clear operational boundaries where full automation is not yet mature.