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CktGNN: Circuit Graph Neural Network for Electronic Design Automation

Zehao DongWeidong CaoMuhan ZhangDacheng TaoYixin ChenXuan Zhang

article2023ICLR78 citations

Introduces a nested graph neural network framework and an open 10,000-circuit dataset that simultaneously automate analog circuit topology generation and transistor sizing, outperforming expert manual designs.

Peking UniversityUniversity of SydneyWashington University in St. Louisautomationbipartite graphscircuit topology
arXiv: 2308.16406zehao-dong/CktGNN
Cover for CktGNN: Circuit Graph Neural Network for Electronic Design Automation

Abstract

The electronic design automation of analog circuits has been a longstanding challenge in the integrated circuit field due to the huge design space and complex design trade-offs among circuit specifications. In the past decades, intensive research efforts have mostly been paid to automate the transistor sizing with a given circuit topology. By recognizing the graph nature of circuits, this paper presents a Circuit Graph Neural Network (CktGNN) that simultaneously automates the circuit topology generation and device sizing based on the encoder-dependent optimization subroutines. Particularly, CktGNN encodes circuit graphs using a two-level GNN framework (of nested GNN) where circuits are represented as combinations of subgraphs in a known subgraph basis. In this way, it significantly improves design efficiency by reducing the number of subgraphs to perform message passing. Nonetheless, another critical roadblock to advancing learning-assisted circuit design automation is a lack of public benchmarks to perform canonical assessment and reproducible research. To tackle the challenge, we introduce Open Circuit Benchmark (OCB), an open-sourced dataset that contains 1010K distinct operational amplifiers with carefully-extracted circuit specifications. OCB is also equipped with communicative circuit generation and evaluation capabilities such that it can help to generalize CktGNN to design various analog circuits by producing corresponding datasets. Experiments on OCB show the extraordinary advantages of CktGNN through representation-based optimization frameworks over other recent powerful GNN baselines and human experts' manual designs. Our work paves the way toward a learning-based open-sourced design automation for analog circuits. Our source code is available at \url{this https URL}.

Topics

automationbipartite graphscircuit topologydesign automationgraph neural networksintegrated circuitsoptimizationsource codessubroutinestopology

Table of Contents

  • 1 Introduction
  • 2 Related Works
  • 2.1 Graph Neural Networks
  • 2.2 Automated Analog Circuit Design
  • 3 Circuit Graph Neural Network
  • 3.1 Two-level GNN Framework with a Subgraph Basis
  • 3.2 The CktGNN Model
  • 3.3 Discussions
  • 4 Open Circuit Benchmark
  • 5 Experiments
  • 5.1 Dataset, Baselines, and Tasks
  • 5.2 Predictive Performance and Topology Reconstruction Accuracy
  • 5.3 Circuit Encoding Efficiency
  • 5.4 Effectiveness in Real-World Electronic Circuit Design
  • 6 Conclusion and Discussions
  • 7 Acknowledgement
  • 8 Reproducibility Statement
  • References
  • A Operational Amplifiers (Circuits) and the Corresponding Subgraph Basis
  • B Expressive Ability of Two-level GNN with a Subgraph Bsis
  • C Proof of Theorem
  • D Experiment Details and Additional Results
  • E More Details about Training and Evaluation
  • F More Details about Decoder
  • G Recent Update of OCB Database

Knowls

  1. Knowl 1 — Circuit Graph Neural Network Architecture

    model/method

    The Circuit Graph Neural Network (CktGNN) is a two-level graph neural network designed to encode directed acyclic circuit graphs into continuous vector embeddings for simultaneous topology generation and device sizing. Given a circuit graph G=(V,E)G = (V, E) transformed into a meta-graph G′=(V′,E′)G' = (V', E') where each node v′∈V′v' \in V' represents a non-overlapping functional subgraph gv′g_{v'} from a predefined ordered subgraph basis B\mathbb{B}, CktGNN processes the circuit in two hierarchical stages:

    1. Inner Level GNNs: Each subgraph gv′g_{v'} is treated as an undirected graph. Multiple layers of undirected message passing are executed simultaneously across devices within gv′g_{v'}, followed by a graph pooling operation to summarize the internal structure and device parameters into a fixed-length subgraph embedding hv′h_{v'}.

    2. Outer Level GNN: Directed message passing is performed across the meta-nodes in G′G' following the topological order of the directed acyclic graph. For each node v′∈V′v' \in V', the incoming aggregated message av′a_{v'} and updated hidden state zv′z_{v'} are computed as:

    av′=∑u′∈N(v′)g(zu′)⊙m(zu′)a_{v'} = \sum_{u' \in \mathcal{N}(v')} g(z_{u'}) \odot m(z_{u'})

    zv′=GRU(concat(xv′′,hv′),av′)z_{v'} = \text{GRU}(\text{concat}(x'_{v'}, h_{v'}), a_{v'})

    where N(v′)\mathcal{N}(v') is the set of predecessor nodes with directed edges into v′v', zu′z_{u'} is the hidden state vector of predecessor u′u', g(⋅)g(\cdot) is a gating neural network, m(⋅)m(\cdot) is a feedforward mapping network, ⊙\odot denotes element-wise multiplication, xv′′x'_{v'} is the one-hot categorical encoding of the subgraph type in B\mathbb{B}, and hv′h_{v'} is the subgraph representation learned by the inner GNNs.

    The overall circuit embedding is given by the final hidden state zvout′z_{v'_{\text{out}}} of the designated circuit output meta-node.

  2. Knowl 2 — Ordered Subgraph Basis for Graph Transformation

    definition

    An ordered subgraph basis B={g1,g2,…,gK}\mathbb{B} = \{g_1, g_2, \dots, g_K\} is a finite collection of KK predefined subgraphs equipped with a strict total ordering oo. For any pair of distinct subgraphs gi,gj∈Bg_i, g_j \in \mathbb{B}, the ordering satisfies gi<gj  ⟺  o(gi)<o(gj)g_i < g_j \iff o(g_i) < o(g_j).

    When decomposing an input circuit graph G=(V,E)G = (V, E) into subgraphs using basis B\mathbb{B}:

    1. For any node v∈Vv \in V, if vv belongs to multiple candidate subgraphs g1v,…,gmv∈Bg_1^v, \dots, g_m^v \in \mathbb{B}, the selected subgraph for inner representation learning is chosen by maximal order:

    ghv=arg⁡max⁡i∈{1,…,m}o(giv)g_h^v = \arg\max_{i \in \{1, \dots, m\}} o(g_i^v)

    1. If two connected nodes u,v∈Vu, v \in V select the same subgraph gh∈Bg_h \in \mathbb{B}, they are merged into a single meta-node v′v' in the transformed directed acyclic graph G′G', with the learned representation of ghg_h serving as the node feature of v′v' during outer message passing.

  3. Knowl 3 — Injectivity Condition for Subgraph-Basis Graph Transformation

    theoretical result

    Let B\mathbb{B} be an ordered subgraph basis containing every single-node subgraph (subgraphs of size 1). There exists an injective graph transformation f:G→G′f: G \to G' mapping an input directed acyclic graph GG to a transformed graph G′G' whose nodes represent non-overlapping subgraphs from B\mathbb{B}, provided that each subgraph gv′∈Bg_{v'} \in \mathbb{B} contains at most one node that serves as the head (or tail) of an external directed edge whose tail (or head) lies outside gv′g_{v'}.

    The canonical transformation function f(G)=G′f(G) = G' is uniquely determined by two selection rules:

    1. Minimality: Choose the decomposition that minimizes the total number of subgraphs in the transformed graph:

    f(G)=arg⁡min⁡Gi′∣Gi′∣f(G) = \arg\min_{G'_i} |G'_i|

    1. Lexicographical Tie-Breaking: If multiple decompositions Gi′G'_i and Gj′G'_j share the minimum cardinality KK, each decomposition is represented as a tuple of subgraph orders ti=(o(gi,1),…,o(gi,K))t_i = (o(g_{i,1}), \dots, o(g_{i,K})) sorted according to basis order oo. The function selects:

    f(G)={Gi′if ti>tjGj′if tj>tif(G) = \begin{cases} G'_i & \text{if } t_i > t_j \\ G'_j & \text{if } t_j > t_i \end{cases}

    where >> denotes lexicographical comparison.

    Under these conditions, the transformation ff is injective, guaranteeing that non-isomorphic circuit structures map uniquely to distinct transformed graph representations.

  4. Knowl 4 — Expressive Power of Two-Level Subgraph-Basis Graph Neural Networks

    theoretical result

    For a given graph family, by selecting an appropriate ordered subgraph basis B\mathbb{B} and total ordering function oo, the expressive power of the two-level GNN framework satisfies:

    1. It is strictly more expressive than standard 1-hop message passing GNNs (which are upper-bounded by the 1-dimensional Weisfeiler-Lehman / 1-WL isomorphism test).
    2. It achieves the same expressive power as the Nested Graph Neural Network (NGNN) framework in distinguishing nn-node rr-regular graphs.

    When the subgraph basis B\mathbb{B} contains all subgraphs of depth 1, the framework reduces to standard message passing. When B\mathbb{B} is augmented with rooted subgraphs of height k>1k > 1, the inner GNNs extract higher-order distance and substructure features. Restricting B\mathbb{B} to a domain-specific set of functional circuit building blocks retains this high representational capacity while drastically pruning the combinatorial topology search space.

  5. Knowl 5 — Circuit-to-DAG Abstraction and Subgraph Basis for Operational Amplifiers

    model/method

    To map multi-stage operational amplifiers (Op-Amps) into directed acyclic graphs (DAGs) without generating cycles:

    1. Behavioral Modeling: Each single-stage amplifier within the circuit is represented by its small-signal behavioral equivalent: a voltage-controlled current source (VCCS) characterized by transconductance gmg_m, paired with an equivalent parasitic resistor RR and capacitor CC.

    2. Graph Mapping: Electrical junction nodes (input, output, intermediate connection nodes, and ground) form graph vertices. Sub-circuit modules and compensation paths connecting these junctions form directed graph edges. Both feedforward and feedback paths are oriented in the forward signal flow direction, distinguishing feedback by negative polarity in device transconductance (e.g., +gm+g_m vs. −gm-g_m).

    3. Subgraph Basis B\mathbb{B}: The basis comprises 24 connection patterns:

    • Single passive component: RR or CC (2 types).
    • Paired passives: RR and CC connected in series or in parallel (2 types).
    • Single active stage: single-stage Op-Amp (gmg_m) with positive/negative polarity and feedforward/feedback direction (4 types).
    • Hybrid active-passive stage: gmg_m combined with RR or CC in series or parallel combinations (16 types).
    1. Basis Ordering Rules: Subgraphs of size 1 are ordered o(gm)>o(R)>o(C)o(g_m) > o(R) > o(C), with positive feedforward prioritizing over negative feedback. Subgraphs of size greater than 1 are ordered primarily by the number of constituent components, then by connection topology (parallel prior to series), and finally lexicographically by component types.

  6. Knowl 6 — Variational Autoencoder and Auto-Regressive Decoder for Circuit Generation

    model/method

    Simultaneous generation of circuit topology and device sizing is achieved using a Variational Autoencoder (VAE) architecture with CktGNN as the encoder.

    Training Objective: The VAE is optimized by minimizing:

    LVAE=Lrecon+αDKL(q(z∣G) ∥ p(z))\mathcal{L}_{\text{VAE}} = \mathcal{L}_{\text{recon}} + \alpha D_{\text{KL}}(q(z|G) \,\|\, p(z))

    where p(z)=N(0,I)p(z) = \mathcal{N}(0, I), q(z∣G)=N(μ,diag(σ2))q(z|G) = \mathcal{N}(\mu, \text{diag}(\sigma^2)) is parameterized by two fully connected layers operating on the CktGNN graph embedding zvout′z_{v'_{\text{out}}}, and α=0.005\alpha = 0.005.

    Auto-Regressive Decoder: Given a latent sample z∼N(0,I)z \sim \mathcal{N}(0, I), the decoder reconstructs the transformed circuit DAG G′G' step-by-step:

    1. An initial state h0=MLP(z)h_0 = \text{MLP}(z) is computed.
    2. For the ii-th generated subgraph meta-node vi′v'_i, an MLP fsubg(hvi−1′)f_{\text{subg}}(h_{v'_{i-1}}) outputs the probability distribution over subgraph types in basis B\mathbb{B}.
    3. Once the subgraph type is selected, dedicated MLPs predict the continuous device sizing parameters (resistance, capacitance, transconductance) of all components within vi′v'_i conditioned on the hidden state.
    4. For each previously generated meta-node vj′v'_j (j<ij < i), an MLP fedge(hvj′,hvi′)f_{\text{edge}}(h_{v'_j}, h_{v'_i}) predicts the existence of a directed edge (vj′,vi′)(v'_j, v'_i).
    5. Subgraph representations and hidden states are updated via CktGNN directed message passing until an output terminal node is emitted.

    Validity Filtering: A generated circuit DAG is considered valid if: (1) it contains exactly one input node and one output node; (2) it is strictly acyclic; and (3) no passive resistor or capacitor sits directly on the main feedforward amplification path.

  7. Knowl 7 — Open Circuit Benchmark (OCB) Suite

    experimental setup

    The Open Circuit Benchmark (OCB) is an open-source dataset and simulation platform designed for evaluating analog circuit topology synthesis and transistor sizing algorithms.

    Dataset Specifications:

    • Circuits: 10,000 operational amplifier (Op-Amp) designs generated across multi-stage topologies and compensation networks.
    • Component Parameter Ranges:
      • Resistors: R∈[105,107] ΩR \in [10^5, 10^7]\ \Omega
      • Capacitors: C∈[10−14,10−12] FC \in [10^{-14}, 10^{-12}]\ \text{F}
      • Single-stage transconductance: gm∈[10−4,10−2] Sg_m \in [10^{-4}, 10^{-2}]\ \text{S}
    • Simulated Metrics: Extracted via automated SPICE netlist simulation:
      • DC Gain (Gain\text{Gain}, in dB)
      • Bandwidth (BW\text{BW}, in Hz)
      • Phase Margin (PM\text{PM}, in degrees)
      • Figure of Merit (FoM\text{FoM}), an aggregate metric combining Gain, BW, and PM to assess overall operational amplifier quality.
    • Dataset Variants:
      • Ckt-Bench101: 10,000 successfully simulated circuit designs with non-divergent specifications.
      • Ckt-Bench301: Tabular surrogate search space benchmark specifically formatted for testing black-box and Bayesian optimization algorithms (such as Bohamiann and DNGO) without requiring live simulator execution.

  8. Knowl 8 — Performance on Circuit Property Prediction and Topology Reconstruction

    data/table

    The representation quality of CktGNN was evaluated by using learned graph embeddings to train Sparse Gaussian Process (SGP) regression models predicting circuit performance metrics (DC Gain, Bandwidth BW, Phase Margin PM, Figure of Merit FoM) and by evaluating topology reconstruction accuracy within a VAE framework on the Open Circuit Benchmark.

    Gain BW PM FoM Recon
    Model RMSE ↓\downarrow Pearson's r↑r \uparrow RMSE ↓\downarrow Pearson's r↑r \uparrow RMSE ↓\downarrow Pearson's r↑r \uparrow RMSE ↓\downarrow Pearson's r↑r \uparrow Acc ↑\uparrow
    CktGNN 0.607 ±\pm 0.003 0.791 ±\pm 0.002 0.873 ±\pm 0.003 0.479 ±\pm 0.001 0.973 ±\pm 0.002 0.217 ±\pm 0.001 0.854 ±\pm 0.003 0.491 ±\pm 0.002 0.397
    PACE 0.644 ±\pm 0.003 0.762 ±\pm 0.002 0.896 ±\pm 0.003 0.442 ±\pm 0.001 0.970 ±\pm 0.003 0.226 ±\pm 0.001 0.889 ±\pm 0.003 0.423 ±\pm 0.001 0.306
    DAGNN 0.695 ±\pm 0.002 0.707 ±\pm 0.001 0.881 ±\pm 0.002 0.453 ±\pm 0.001 0.969 ±\pm 0.003 0.231 ±\pm 0.002 0.877 ±\pm 0.003 0.442 ±\pm 0.001 0.289
    D-VAE 0.681 ±\pm 0.003 0.739 ±\pm 0.001 0.914 ±\pm 0.002 0.394 ±\pm 0.001 0.956 ±\pm 0.003 0.301 ±\pm 0.002 0.897 ±\pm 0.003 0.374 ±\pm 0.001 0.271
    GCN 0.976 ±\pm 0.003 0.140 ±\pm 0.002 0.970 ±\pm 0.003 0.236 ±\pm 0.001 0.993 ±\pm 0.002 0.171 ±\pm 0.001 0.974 ±\pm 0.003 0.217 ±\pm 0.001 0.058
    GIN 0.890 ±\pm 0.003 0.352 ±\pm 0.001 0.926 ±\pm 0.002 0.251 ±\pm 0.001 0.985 ±\pm 0.004 0.187 ±\pm 0.002 0.910 ±\pm 0.003 0.284 ±\pm 0.001 0.051
    NGNN 0.882 ±\pm 0.004 0.433 ±\pm 0.002 0.933 ±\pm 0.003 0.247 ±\pm 0.001 0.984 ±\pm 0.004 0.196 ±\pm 0.002 0.926 ±\pm 0.002 0.267 ±\pm 0.001 0.068
    Pathformer 0.816 ±\pm 0.003 0.529 ±\pm 0.001 0.895 ±\pm 0.002 0.410 ±\pm 0.001 0.967 ±\pm 0.002 0.297 ±\pm 0.001 0.887 ±\pm 0.002 0.391 ±\pm 0.001 0.081

    CktGNN achieves the lowest RMSE and highest Pearson correlation on Gain (r=0.791r=0.791), BW (r=0.479r=0.479), and FoM (r=0.491r=0.491), while substantially outperforming all baselines in topology reconstruction accuracy (0.3970.397 vs. 0.3060.306 for PACE and ≤0.081\le 0.081 for undirected GNNs). The two-level decomposition encodes internal device interactions through inner GNNs while compressing the topology search space.

  9. Knowl 9 — Circuit Generation Validity Rates and Bayesian Optimization Performance

    data/table

    The effectiveness of CktGNN in real-world circuit design was tested by measuring the proportion of generated valid DAGs, valid circuits, and novel valid circuits from 1,000 random latent space samples decoded 10 times, alongside the maximum Figure of Merit (FoM) achieved using batch Bayesian Optimization (batch size 50, expected improvement heuristic, 10 iterations) over the latent space.

    Methods Valid DAGs (%) ↑\uparrow Valid circuits (%) ↑\uparrow Novel circuits (%) ↑\uparrow BO (FoM) ↑\uparrow
    CktGNN 98.92 98.92 92.29 33.436447
    PACE 83.12 75.52 97.14 33.274162
    DAGNN 83.10 74.21 97.19 33.274162
    D-VAE 82.12 73.93 97.15 32.377778
    GCN 81.02 72.03 97.01 31.624473
    GIN 80.92 73.17 96.88 31.624473
    NGNN 82.17 73.22 95.29 32.282656
    Graphormer 82.81 72.70 94.80 32.282656

    By constraining generation to valid subgraphs in basis B\mathbb{B}, CktGNN-VAE generates valid circuits at a rate of 98.92% (matching its valid DAG rate), compared to 72.03%–75.52% for baselines where unconstrained device connections often produce ill-posed analog topologies. In downstream Bayesian optimization, CktGNN identifies circuits with the highest overall FoM (33.43644733.436447).

Coverage note — Hardware runtime bar charts (Figure 3) and extended tabular evaluations on the updated Ckt-Bench101/301 datasets (Tables 3-5 in Appendix G) were summarized into the benchmark setup and main data tables to focus on core architectural and empirical contributions.

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Citation

MLA
Dong, Z., et al. “CktGNN: Circuit Graph Neural Network for Electronic Design Automation”. arXiv, 2023, http://arxiv.org/abs/2308.16406v2.
APA
Dong, Z., Cao, W., Zhang, M., Tao, D., Chen, Y., & Zhang, X. (2023). CktGNN: Circuit Graph Neural Network for Electronic Design Automation. arXiv. http://arxiv.org/abs/2308.16406v2
Chicago
Dong, Z., W. Cao, M. Zhang, D. Tao, Y. Chen, and X. Zhang. 2023. “CktGNN: Circuit Graph Neural Network for Electronic Design Automation”. arXiv. http://arxiv.org/abs/2308.16406v2.
Harvard
Dong, Z. et al. (2023) “CktGNN: Circuit Graph Neural Network for Electronic Design Automation”, arXiv [Preprint]. Available at: http://arxiv.org/abs/2308.16406v2.
Vancouver
1. Dong Z, Cao W, Zhang M, Tao D, Chen Y, Zhang X (2023) CktGNN: Circuit Graph Neural Network for Electronic Design Automation. arXiv

BibTeX

@article{dong2023cktgnn,
  title = {CktGNN: Circuit Graph Neural Network for Electronic Design Automation},
  author = {Dong, Zehao and Cao, Weidong and Zhang, Muhan and Tao, Dacheng and Chen, Yixin and Zhang, Xuan},
  year = {2023},
  journal = {arXiv},
  url = {http://arxiv.org/abs/2308.16406v2},
  eprint = {2308.16406}
}
Metadata:arXiv

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