Versatile Multi-stage Graph Neural Network for Circuit Representation

Shuwen YangZhihao YangDong LiYingxue ZhangZhanguang ZhangGuojie SongJianye Hao

article2022NeurIPS52 citations

Proposes Circuit Graph and Circuit GNN to fuse topological and geometric chip design data into a unified representation, achieving state-of-the-art accuracy across multiple EDA stages while delivering a tenfold speedup in congestion prediction.

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Modern integrated circuit design faces increasing complexity, making traditional design automation workflows time-consuming and costly. To accelerate development and prevent costly manufacturing defects, chip designers rely on predictive machine learning models to detect routing congestion and estimate wiring performance early in the design cycle. However, current artificial intelligence approaches are fragmented. Purely topological methods analyze structural connectivity in netlists but fail to utilize spatial data available after placement, while computer vision-based geometric methods rely on spatial grid images and cannot operate during earlier logic synthesis stages. This lack of a unified representation creates performance bottlenecks and restricts machine learning models from generalizing across multiple design stages and tasks.

To address this challenge, the article introduces Circuit Graph, a unified heterogeneous graph structure, and Circuit GNN, an efficient neural network framework designed to process it. The primary objective is to demonstrate a versatile circuit representation method that seamlessly integrates logical circuit topology and physical layout geometry, providing superior prediction accuracy and computational efficiency across both logic synthesis and placement stages.

The evaluated approach models circuits as bipartite graphs containing cell and net nodes connected by topological edges, while adding geometric edges between spatially adjacent cells when physical placement coordinates are available. The neural network applies distinct message-passing mechanisms over both edge types and fuses the resulting representations using pooling operations. To maintain linear computational complexity relative to circuit size, the authors use a shifted-window technique to constrain geometric edge connections. The authors evaluated the framework on standard benchmark datasets (ISPD2011 and DAC2012) using established placement tools and routers across multiple predictive tasks, comparing it against conventional graph neural networks, computer vision baselines, and industry-specific predictive models.

The findings show that the proposed framework consistently outperforms existing state-of-the-art methods while dramatically reducing computational overhead. In the logic synthesis stage, the model improves average grid-level congestion prediction accuracy by 16.7% over existing topological methods. In the placement stage, it achieves a 5.6% gain in congestion prediction accuracy while delivering a tenfold speedup compared to leading models. For net wirelength estimation, the model reduces prediction error by 16.9%. Furthermore, transfer learning experiments confirm that features learned during congestion prediction transfer effectively to wirelength estimation with minimal fine-tuning, outperforming competing architectures in cross-task adaptability.

These results demonstrate that unifying topological and spatial circuit data into a single neural framework significantly enhances predictive power without introducing exponential runtime penalties. Operationally, earlier and more accurate congestion and wirelength forecasting enables an industry shift toward earlier design optimization, commonly referred to as shifting left. This reduces iterative redesign cycles, cuts production timelines, lowers design costs, and prevents the fabrication of flawed semiconductor chips.

Based on these findings, engineering teams developing electronic design automation pipelines should consider adopting unified heterogeneous graph structures to standardize circuit feature representations across pre-placement and post-placement toolchains. Organizations should pursue pilot integrations into global placement and logic synthesis workflows to validate speedups in production environments. Further engineering work is needed to bridge the deployment gap between research algorithms and commercial electronic design automation tool suites. Additionally, researchers should explore extending the representation to earlier design representations, such as high-level data-flow graphs and logic-level graphs, where node and edge semantics diverge from standard netlists.

Huawei Nanjing University Peking University School of Software and Microelectronics automation congestion deep learning multi-stage graph neural network circuit representation circuit graph

Yang et al (2022).pdf

Paper: Semi-Supervised Classification with Graph Convolutional Networks, Thomas N. Kipf et al. (2017). Establishes foundational spatial graph convolutional networks that the source adapts to process circuit netlist topologies.
Paper: Graph Transformer Networks, Seongjun Yun et al. (2019). Introduces graph neural network architectures for heterogeneous graphs containing multiple node and relation types, providing the structural foundation for bipartite circuit representations.
Paper: Dynamic Edge-Conditioned Filters in Convolutional Neural Networks on Graphs, Martin Simonovsky et al. (2017). Introduces edge-conditioned convolutions that inform how geometric and spatial attributes are incorporated into graph message-passing operations.
Paper: The Graph Neural Network Model, Franco Scarselli et al. (2009). Provides the seminal theoretical formulations of graph neural networks and node-level message passing underpinning modern circuit learning architectures.
Paper: How Powerful are Graph Neural Networks?, Keyulu Xu et al. (2019). Formalizes the expressive power and aggregation mechanics of graph neural networks, motivating the design of specialized bipartite and multi-stage circuit encoders.

Paper: CktGNN: Circuit Graph Neural Network for Electronic Design Automation, Zehao Dong et al. (2023). Extends graph neural network representations of electronic circuits to automated topology generation and sizing in analog electronic design automation.
Paper: BetterV: Controlled Verilog Generation with Discriminative Guidance, Zehua Pei et al. (2024). Applies machine learning to earlier electronic design automation stages by generating Verilog code optimized for downstream logic synthesis workflows.

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Abstract

Due to the rapid growth in the scale of circuits and the desire for knowledge transfer from old designs to new ones, deep learning technologies have been widely exploited in Electronic Design Automation (EDA) to assist circuit design. In chip design cycles, we might encounter heterogeneous and diverse information sources, including the two most informative ones: the netlist and the design layout. However, handling each information source independently is sub-optimal. In this paper, we propose a novel way to integrate the multiple information sources under a unified heterogeneous graph named Circuit Graph, where topological and geometrical information is well integrated. Then, we propose Circuit GNN to fully utilize the features of vertices, edges as well as heterogeneous information during the message passing process. It is the first attempt to design a versatile circuit representation that is compatible across multiple EDA tasks and stages. Experiments on the two most representative prediction tasks in EDA show that our solution reaches state-of-the-art performance in both logic synthesis and global placement chip design stages. Besides, it achieves a 10x speed-up on congestion prediction compared to the state-of-the-art model.

Topics

automation congestion deep learning design automation graph neural networks knowledge transfer learning technologies logic synthesis electronic designs convolutional neural networks

Keywords

multi-stage graph neural network circuit representation circuit graph unified heterogeneous graph net wirelength prediction circuit featurization topological message passing circuit layout

1 Introduction
2 Related Work
2.1 Topological Methods
2.2 Geometrical Methods
3 Circuit Graph
3.1 Circuit Featurization
3.2 Definition of Circuit Graph
4 Circuit GNN
4.1 Overview
4.2 Topo-Geom Message-passing
4.3 Task-adaptive Readout
5 Experiments
5.1 Tasks and Datasets
5.2 Baselines and Settings
5.3 Result of Congestion Prediction
5.4 Result of Net Wirelength Prediction
5.5 Result of Transfer Task
6 Conclusion and Future Work
References

Knowls

Knowl 1 — Circuit Graph Heterogeneous Representation
definition
A circuit design is formulated as a unified heterogeneous graph called Circuit Graph $G = \{V, U, \mathcal{E}_T, \mathcal{E}_G, X_V, X_U, X_{\mathcal{E}_T}, X_{\mathcal{E}_G}\}$ , where:
- $V$ is the set of standard electronic cells, with cell feature matrix $X_V$ containing cell dimensions (size) and cell degree (number of connected nets).
- $U$ is the set of nets (hyper-edges interconnecting cells), with net feature matrix $X_U$ containing net bounding span and net degree (number of connected cells).
- $\mathcal{E}_T \subseteq V \times U$ is the set of topological edges (pins) representing bipartite connections between cells and nets. Its feature matrix $X_{\mathcal{E}_T}$ records cell-net interaction attributes, including pin signal direction (input/output).
- $\mathcal{E}_G \subseteq V \times V$ is the set of geometrical edges connecting geometrically proximal cell pairs after placement. Its feature matrix $X_{\mathcal{E}_G}$ contains pairwise Euclidean distances.
To construct $\mathcal{E}_G$ in $O(|V|)$ time during or after the placement stage, the circuit layout is partitioned into shifted rectangular windows of size $(w_x, w_y)$ , and each cell is linked to at most $c$ (link capacity) neighboring cells residing within the same window. For pre-placement stages (such as logic synthesis) where geometric placement coordinates $(p_x, p_y)$ are unavailable, $\mathcal{E}_G = \emptyset$ , rendering the graph fully backward-compatible with purely topological circuit netlists.
Knowl 2 — Circuit GNN Topo-Geom Message-Passing Formulation
model/method
Circuit GNN propagates topological and geometrical signals across distinct edge types using a dedicated two-branch message-passing mechanism at layer $l$ :
1. Topological Cell-to-Net Propagation ( $V \to U$ ): $\Phi_{msg}^{V \xrightarrow{\mathcal{E}_T} U}\left(\{(h_v^{V,(l)}, h_{(v,u)}^{\mathcal{E}_T}) \mid (v,u) \in \mathcal{E}_T\}\right) = \sum_{(v,u) \in \mathcal{E}_T} \left(W_{\mathcal{E}_T \to U} h_{(v,u)}^{\mathcal{E}_T}\right) \odot \left(W_{V \to U} h_v^{V,(l)}\right)$ where $h_v^{V,(l)} \in \mathbb{R}^{F_V}$ is the representation of cell $v$ , $h_{(v,u)}^{\mathcal{E}_T} \in \mathbb{R}^{F_{\mathcal{E}_T}}$ is the fixed embedding of topo-edge $(v,u)$ , $W_{\mathcal{E}_T \to U} \in \mathbb{R}^{F_U \times F_{\mathcal{E}_T}}$ and $W_{V \to U} \in \mathbb{R}^{F_U \times F_V}$ are learnable weight matrices, and $\odot$ denotes element-wise multiplication.
2. Topological Net-to-Cell Propagation ( $U \to V$ ): $\Phi_{msg}^{U \xrightarrow{\mathcal{E}_T} V}\left(\{h_u^{U,(l)} \mid (v,u) \in \mathcal{E}_T\}\right) = \sum_{(v,u) \in \mathcal{E}_T} W_{U \to V} h_u^{U,(l)}$ where $h_u^{U,(l)} \in \mathbb{R}^{F_U}$ is the representation of net $u$ , and $W_{U \to V} \in \mathbb{R}^{F_V \times F_U}$ is a learnable projection matrix.
3. Geometrical Cell-to-Cell Convolution ( $V \xrightarrow{\mathcal{E}_G} V$ ): $\Phi_{msg}^{V \xrightarrow{\mathcal{E}_G} V}\left(\{(h_{v^*}^{V,(l)}, h_{(v,v^*)}^{\mathcal{E}_G}) \mid (v,v^*) \in \mathcal{E}_G\}\right) = \sum_{(v,v^*) \in \mathcal{E}_G} \left(a^\top h_{(v,v^*)}^{\mathcal{E}_G}\right) \cdot W_{V \to V} h_{v^*}^{V,(l)}$ where $h_{(v,v^*)}^{\mathcal{E}_G} \in \mathbb{R}^{F_{\mathcal{E}_G}}$ is the embedding of geom-edge $(v,v^*)$ , $a \in \mathbb{R}^{F_{\mathcal{E}_G}}$ is a learnable weight vector computing edge attention weights, and $W_{V \to V} \in \mathbb{R}^{F_V \times F_V}$ is a learnable cell-to-cell projection matrix.
Knowl 3 — Message Fusion and Representation Updating in Circuit GNN
model/method
In each Topo-Geom message-passing layer $l \in \{0, \dots, L-1\}$ , Circuit GNN fuses the geometrical and topological messages for cells and updates node hidden states:
1. Message Fusion: $M_V^{(l)} = \text{MaxPooling}\left(M_V^{(l),geom}, M_V^{(l),topo}\right)$ where $M_V^{(l),geom}$ and $M_V^{(l),topo}$ denote the aggregated geometrical and topological messages received by cells $V$ . When geom-edges are absent (such as in pre-placement stages where $\mathcal{E}_G = \emptyset$ ), $M_V^{(l)} = M_V^{(l),topo}$ .
2. State Updates:
ight) = H_V^{(l)} + \tanh\left(M_V^{(l)} ight)$$ $$H_U^{(l+1)} = \Phi_{update}\left(H_U^{(l)}, M_U^{(l)} ight) = H_U^{(l)} + \tanh\left(M_U^{(l)} ight)$$ where $H_V^{(l)}$ and $H_U^{(l)}$ denote the matrix of hidden embeddings for all cells and nets at layer $l$, and $M_U^{(l)}$ is the topological message received by nets from connected cells. Initial embeddings $H_V^{(0)}, H_U^{(0)}, H_{\mathcal{E}_T}, H_{\mathcal{E}_G}$ are generated by feeding raw features $X_V, X_U, X_{\mathcal{E}_T}, X_{\mathcal{E}_G}$ through separate Multi-Layer Perceptrons (MLPs).
Knowl 4 — Task-Adaptive Readout Mechanisms for Circuit Downstream Predictions
model/method
After $L$ layers of message-passing in Circuit GNN, final representations $H_V^{(L)}$ and $H_U^{(L)}$ are mapped to target predictions via task-specific readout layers:
- Cell-Level Prediction (e.g., cell-level routing congestion): $\hat{y}_{cell} = \text{MLP}\left(H_V^{(L)} \oplus X_V\right)$ where $\oplus$ represents feature concatenation with raw cell features $X_V$ .
- Net-Level Prediction (e.g., net wirelength estimation): $\hat{y}_{net} = \text{MLP}\left(H_U^{(L)} \oplus X_U\right)$ where $X_U$ denotes the raw net features.
- Grid-Level Prediction (e.g., spatial layout congestion on a layout divided into $C_x \times C_y$ grids): $\hat{y}_{grid} = \text{MLP}\left(\hat{M} H_V^{(L)}\right)$ where $\hat{M} \in \mathbb{R}^{C_x \times C_y \times |V|}$ is a layout transformation matrix that performs spatial mean-pooling over all cells located within grid $(i, j)$ , satisfying $\sum_{k=1}^{|V|} \hat{M}_{i,j,k} = 1$ for all valid grid locations $(i,j)$ containing cells.
Knowl 5 — Linear Computational Complexity of Circuit Graph and Circuit GNN
theoretical result
For a circuit design with $|V|$ cells, $|U|$ nets, and $|P|$ pins:
1. Graph Construction Complexity: Constructing topo-edges $\mathcal{E}_T = P$ takes $O(|P|)$ time. Geometrical edges $\mathcal{E}_G$ are constructed using shifted windows with link capacity $c$ , requiring $O(|V|)$ time rather than naive all-pair distance computation $O(|V|^2)$ . The total graph construction time complexity is $O(|V| + |U| + |P|)$ .
2. Inference Complexity Per Layer: For cell feature dimension $F_V$ , net feature dimension $F_U$ , topo-edge feature dimension $F_{\mathcal{E}_T}$ , and geom-edge feature dimension $F_{\mathcal{E}_G}$ :
- Cell-to-net topological message passing: $O(|\mathcal{E}_T|(F_{\mathcal{E}_T} F_U + F_V F_U + F_U))$
- Net-to-cell topological message passing: $O(|\mathcal{E}_T| F_U F_V)$
- Cell-to-cell geometrical message passing: $O(|\mathcal{E}_G|(F_{\mathcal{E}_G} + F_V^2))$
- Fusion (MaxPooling) and state updates: $O(|V| F_V + |U| F_U)$
Since hidden dimensions are fixed constants, $|\mathcal{E}_T| = O(|P|)$ , and $|\mathcal{E}_G| = O(|V|)$ , the overall inference time complexity of Circuit GNN is $O(|V| + |U| + |P|)$ per layer, which scales strictly linearly with circuit size.

Knowl 6 — Congestion Prediction in the Logic Synthesis Stage

data/table

In the pre-placement logic synthesis stage where spatial layout coordinates are unavailable (evaluated on ISPD2011 benchmarks with global router NCTU-GR 2.0 ground truth and $\mathcal{E}_G = \emptyset$ ), Circuit GNN outperforms standard GNNs and EDA-specific models on both cell-level and grid-level correlation metrics:

Baseline	Time (s/epoch)	Cell-level			Grid-level
Baseline	Time (s/epoch)	pearson	spearman	kendall	pearson	spearman	kendall
GCN	9.43	0.777	0.265	0.199	0.221	0.366	0.260
GraphSAGE	11.79	0.776	0.252	0.188	0.208	0.375	0.268
GAT	13.90	0.777	0.267	0.200	0.215	0.399	0.280
CongestionNet	22.31	0.777	0.269	0.200	0.277	0.394	0.280
MPNN	116.24	0.780	0.289	0.217	0.292	0.458	0.319
Ours (w/o. geom.)	21.62	0.779	0.289	0.217	0.315	0.468	0.329

Circuit GNN (w/o. geom.) achieves an average grid-level accuracy gain of 16.7% over the EDA-customized model CongestionNet (improving Grid Pearson from 0.277 to 0.315 and Grid Spearman from 0.394 to 0.468) and operates more than $5\times$ faster per training epoch than MPNN (21.62 s vs. 116.24 s).

Knowl 7 — Congestion Prediction in the Placement Stage

data/table

In the placement stage on ISPD2011 benchmarks where cell coordinates from DREAMPlace are available, Circuit GNN fuses topological and geometrical edges to achieve superior correlation compared to vision-based (pix2pix), graph-based (GAT), and lattice-based (LHNN) models:

Baseline	Time (s/epoch)	Cell-level			Grid-level
Baseline	Time (s/epoch)	pearson	spearman	kendall	pearson	spearman	kendall
GAT (w. geom.)	16.21	0.777	0.263	0.197	0.210	0.397	0.279
pix2pix	4.46	-	-	-	0.562	0.554	0.392
LHNN	305.47	-	-	-	0.703	0.695	0.540
Ours (w/o. topo.)	21.54	0.883	0.713	0.573	0.684	0.730	0.536
Ours	27.07	0.887	0.714	0.575	0.697	0.770	0.577

Circuit GNN outperforms the state-of-the-art lattice hypergraph model LHNN on grid-level Spearman rank correlation (0.770 vs. 0.695) and Kendall correlation (0.577 vs. 0.540) while providing a $11.3\times$ training speedup (27.07 s/epoch vs. 305.47 s/epoch). Furthermore, pix2pix and LHNN cannot predict congestion at the cell level, whereas Circuit GNN provides predictions at both cell and grid levels.

Knowl 8 — Net Wirelength Prediction in the Placement Stage

data/table

Net wirelength estimation (predicting $\log_{10}$ of Half-Perimeter Wirelength, HPWL) evaluated on DAC2012 placement designs demonstrates the predictive accuracy of Circuit GNN:

Baseline	Time (s/epoch)	pearson	spearman	kendall	MAE $\downarrow$	RMSE $\downarrow$
MLP	2.22	0.493	0.547	0.415	0.626	0.819
Net2f	10.42	0.517	0.635	0.525	0.615	0.825
Net2a	19.83	0.632	0.656	0.553	0.614	0.821
LHNN	260.00	0.801	0.796	0.603	0.581	0.780
Ours	14.79	0.848	0.835	0.646	0.483	0.683

Circuit GNN achieves an average error reduction of 16.9% over LHNN (MAE 0.483 vs. 0.581; RMSE 0.683 vs. 0.780) and higher correlation across all metrics (Pearson 0.848 vs. 0.801, Spearman 0.835 vs. 0.796, Kendall 0.646 vs. 0.603), while reducing training time from 260.00 s/epoch to 14.79 s/epoch ( $17.6\times$ faster).

Knowl 9 — Transferability of Circuit GNN Representations Across EDA Tasks

data/table

Models pre-trained on congestion prediction were transferred to predict net wirelength on DAC2012 designs (evaluated at grid level) by freezing the GNN backbone and training a new readout layer (evaluation) or fine-tuning the entire network (fine-tuning) for only $1/5$ of default training epochs:

Baseline	Time (s/epoch)	pearson	spearman	kendall
MLP	2.22	0.493	0.547	0.415
LHNN (evaluate)	192.45	0.689	0.715	0.563
Ours (evaluate)	9.55	0.799	0.811	0.622
LHNN (fine-tune)	248.96	0.805	0.794	0.612
Ours (fine-tune)	14.80	0.842	0.829	0.639
LHNN (fully trained)	260.00	0.801	0.796	0.603
Ours (fully trained)	14.79	0.848	0.835	0.646

Circuit GNN features extracted under the frozen evaluation setting match the performance of LHNN trained from scratch (Pearson 0.799 vs. 0.801, Spearman 0.811 vs. 0.796), while LHNN frozen representations transfer poorly (Pearson 0.689, Spearman 0.715). With fine-tuning, Circuit GNN reaches 0.842 Pearson correlation in 14.80 s/epoch.

Knowl 10 — Limitations of Netlist-Based Circuit GNN Representations
limitation
The Circuit Graph and Circuit GNN framework exhibits two main limitations:
1. Early-Stage Circuit Graph Incompatibility: In design stages prior to logic synthesis, circuits are expressed as Data-Flow Graphs (DFGs) or And-Inverter Graphs (AIGs). The nodes and edges in DFGs and AIGs represent abstract operators and Boolean functional flows rather than physical cells, nets, and pins. Circuit Graph's bipartite cell-net formulation cannot directly represent these graphs without redefining the node and edge semantics.
2. Commercial Tool Integration Gap: While Circuit GNN achieves superior accuracy and inference speeds on benchmark toolchains (DREAMPlace, NCTU-GR), integrating deep learning graph models into production commercial EDA suites (such as Cadence and Synopsys) requires overcoming substantial software infrastructure and deployment gaps.

Coverage note — None was omitted; all key contributions including graph construction, neural architecture, time complexity, congestion and wirelength prediction experiments across synthesis and placement, transferability, and limitations are fully covered.

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Citation

MLA

Yang, S., et al. “Versatile Multi-stage Graph Neural Network for Circuit Representation”. Advances in Neural Information Processing Systems, vol. 35, 2022, pp. 20313–24, https://proceedings.neurips.cc/paper_files/paper/2022/file/7fa548155f40c014372146be387c4f6a-Paper-Conference.pdf.

APA

Yang, S., Yang, Z., Li, D., Zhang, Y., Zhang, Z., Song, G., & Hao, J. (2022). Versatile Multi-stage Graph Neural Network for Circuit Representation. Advances in Neural Information Processing Systems, 35, 20313–20324. https://proceedings.neurips.cc/paper_files/paper/2022/file/7fa548155f40c014372146be387c4f6a-Paper-Conference.pdf

Chicago

Yang, S., Z. Yang, D. Li, et al. 2022. “Versatile Multi-stage Graph Neural Network for Circuit Representation”. Advances in Neural Information Processing Systems 35: 20313–24. https://proceedings.neurips.cc/paper_files/paper/2022/file/7fa548155f40c014372146be387c4f6a-Paper-Conference.pdf.

Harvard

Yang, S. et al. (2022) “Versatile Multi-stage Graph Neural Network for Circuit Representation”, Advances in Neural Information Processing Systems. Curran Associates, Inc., pp. 20313–20324. Available at: https://proceedings.neurips.cc/paper_files/paper/2022/file/7fa548155f40c014372146be387c4f6a-Paper-Conference.pdf.

Vancouver

1. Yang S, Yang Z, Li D, Zhang Y, Zhang Z, Song G, Hao J (2022) Versatile Multi-stage Graph Neural Network for Circuit Representation. In: Advances in Neural Information Processing Systems. Curran Associates, Inc., pp 20313–20324

BibTeX

@inproceedings{yang2022versatile,
  title = {Versatile Multi-stage Graph Neural Network for Circuit Representation},
  author = {Yang, Shuwen and Yang, Zhihao and Li, Dong and Zhang, Yingxueff and Zhang, Zhanguang and Song, Guojie and Hao, Jianye},
  year = {2022},
  booktitle = {Advances in Neural Information Processing Systems},
  publisher = {Curran Associates, Inc.},
  volume = {35},
  pages = {20313-20324},
  url = {https://proceedings.neurips.cc/paper_files/paper/2022/file/7fa548155f40c014372146be387c4f6a-Paper-Conference.pdf}
}

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Versatile Multi-stage Graph Neural Network for Circuit Representation

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Knowls

Knowl 1 — Circuit Graph Heterogeneous Representation

Knowl 2 — Circuit GNN Topo-Geom Message-Passing Formulation

Knowl 3 — Message Fusion and Representation Updating in Circuit GNN

Knowl 4 — Task-Adaptive Readout Mechanisms for Circuit Downstream Predictions

Knowl 5 — Linear Computational Complexity of Circuit Graph and Circuit GNN

Knowl 6 — Congestion Prediction in the Logic Synthesis Stage

Knowl 7 — Congestion Prediction in the Placement Stage

Knowl 8 — Net Wirelength Prediction in the Placement Stage

Knowl 9 — Transferability of Circuit GNN Representations Across EDA Tasks

Knowl 10 — Limitations of Netlist-Based Circuit GNN Representations

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